IBM and Siemens start research collaboration on nanostack transistor design
IBM and Siemens announced a new research collaboration to advance design and manufacturing methods for IBM’s three-dimensional nanostack transistor architecture. The work combines IBM’s semiconductor-device research with Siemens’ expertise in electronic design automation, process simulation and lithography optimization.
Event / data period: 2026-10-14
Published: · Updated:
The companies plan to develop virtual models to simulate performance, optimize designs and address manufacturing challenges before chips are built. The announcement describes techniques under development, not a production-ready technology.
IBM says its current nanostack design could fit nearly 100 billion transistors in an area the size of a fingernail and is at a 7-angstrom node. These are company-described architecture characteristics; the collaboration did not announce manufacturing yield or a commercial launch timeline.
Data
Research collaboration
IBM and Siemens will research virtual modeling, simulation and lithography for IBM’s nanostack transistor architecture.
- · Occurred
IBM and Siemens start research collaboration on nanostack transistor design
IBM and Siemens will research virtual modeling, simulation and lithography for IBM’s nanostack transistor architecture.
Methodology
The event is IBM’s announcement dated October 14, 2026, of a new research collaboration with Siemens. This is a separate joint research initiative from the previously announced nanostack PDK plan; it does not mean production has begun or performance has been independently validated.
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